• Applications processors for complex OS and user applications.
  • Supports the ARM, Thumb and Thumb-2 instruction sets.
  • Exception
  • DSP
  • Coprocessor
MCR{cond} P15,0,Rd,Cn,Cm,<cp>   ;move from ARM to CP15
MRC{cond} P15,0,Rd,Cn,Cm,<cp>   ;move from CP15 to ARM

1. Pn=P15, and <cpopc>=0
2. Rd can be any ARM register in range R0-R14, R15 should not be used with P15.
3. Cn,Cm,<cp> are used to select a CP15 register, eg. C0,C0,0 = Main ID Register.
  • CP15 Register List
Register Expl.
C0,C0,0 Main ID Register (R)
C0,C0,1 Cache Type and Size (R)
C0,C0,2 TCM Physical Size (R)
C1,C0,0 Control Register (R/W, or R=Fixed)
C2,C0,0 PU Cachability Bits for Data/Unified Protection Region
C2,C0,1 PU Cachability Bits for Instruction Protection Region
C3,C0,0 PU Write-Bufferability Bits for Data Protection Regions
C5,C0,0 PU Access Permission Data/Unified Protection Region
C5,C0,1 PU Access Permission Instruction Protection Region
C5,C0,2 PU Extended Access Permission Data/Unified Protection Region
C5,C0,3 PU Extended Access Permission Instruction Protection Region
C6,C0..C7,0 PU Protection Unit Data/Unified Region 0..7
C6,C0..C7,1 PU Protection Unit Instruction Region 0..7
C7,Cm,Op2 Cache Commands and Halt Function (W)
C9,C0,0 Cache Data Lockdown
C9,C0,1 Cache Instruction Lockdown
C9,C1,0 TCM Data TCM Base and Virtual Size
C9,C1,1 TCM Instruction TCM Base and Virtual Size
C13,Cm,Op2 Misc Process ID registers
C15,Cm,Op2 Misc Implementation Defined and Test/Debug registers
  • GPU
  • arch/arm/include/asm/cputype.h
#define CPUID_TCM       2
  • Clock
  • MPLL用于CPU及其他外围器件,以产生FCLK, HCLK, PCLK三种频率
$MPLL = (2*m*Fin)/(p*2^s)$
$m = (MDIV + 8)$
$p= (PDIV + 2)$
$s = SDIV$
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