Exception/Interrupt

x86

• Interrupt Descriptor Table (IDT)

MIPS32

• Cause Register
  • ExcCode(Exception Code)
    • 0(Interrupt)
    • 8(Syscall Exception)
  • IP(Interrupt Pending)
• EBase Register(exception vector base address)

• Exception
  • Exception Vector
    • Reset, Soft Reset, and NMI exceptions(0xBFC0.0000)
    • EJTAG Debug exceptions(0xBFC0.0480 or 0xFF20.0200)
    • Others
      • Addresses for all other exceptions are a combination of a vector offset and a vector base address.

• Interrupt
  • Interrupt Modes
    • Interrupt Compatibility Mode
      • interrupts are non-vectored and dispatched though exception vector offset 0x180 (if CauseIV = 0) or vector offset 0x200 (if CauseIV = 1).
    • Vectored Interrupt (VI) Mode
      • Vectored Interrupt mode builds on the interrupt compatibility mode by adding a priority encoder to prioritize pending interrupts and to generate a vector with which each interrupt can be directed to a dedicated handler routine.
    • External Interrupt Controller(EIC) Mode
  • Exception Vector Offsets
    • For vectored interrupts (in either VI or EIC interrupt mode), a vector number is produced by the interrupt control logic. This number is combined with IntCtlVS to create the interrupt offset, which is added to 0x200 to create the exception vector offset.

• PIC32MX Family Data Sheet

ARM

• Operational Mode/Exception Mode
• Exception Vectors table
  • When an exception is taken, processor execution is forced to an address that corresponds to the type of exception. These addresses are called the exception vectors. By default, the exception vectors are eight consecutive word-aligned memory addresses, starting at an exception base address.
• AT91 ARM Thumb Microcontrollers Application Note
• ARM Linux 中断代码分析
• arm linux 下中断流程简要分析 — 初始化, 注册中断, 中断处理

• ARMv7
  • Exception entry steps
    1. Push eight registers
    2. Read vector table from memory based on table base + (exception number 4)
    3. Read SP from vector table(On Reset only, updates SP to top of stack from vector table.)
    4. Updates PC(with vector table read location)
    5. Load pipeline(Loads instructions from location pointed to by vector table.)
    6. Update LR

PowerPC

• interrupts are automatic control transfers that occur as a result of an exception
• Exception Vector Prefix Register (EVPR)
  • stores the base address for the exception vector table

• INTERRUPTIONS

• kernel里面的中断代码分析

entry path

• /path to kernel source/arch/x86/kernel/entry_32.S
• /path to kernel source/arch/x86/kernel/irq_32.c
  • do_IRQ
    • irq_enter
    • calling flow handler
      1. desc->handle_irq
      2. generic_handle_irq
         • selects and activates the proper handle_irq function from the IRQ database
    • irq_exit

exit path

IRQ Descriptor

• /path to kernel source/kernel/irq/handle.c
• irq_desc

chip specific functions

• v2.6.17

typedef struct **hw_interrupt_type hw_irq_controller

• v2.6.18+

#define hw_interrupt_type irq_chip
typedef struct **irq_chip hw_irq_controller**

• Flow handling and chip-specific operations are encapsulated here
  • startup
  • enable, disable
  • ack, mask_ack
  • end
  • eoi
  • set_type
    • set_irq_type

irq_handler function/irqaction

• irqreturn_t(old version: void, 2.6: int)
  • IRQ_NONE
  • IRQ_HANDLED
• IRQ_RETVAL(val)
  • If val is non-zero, this macro returns IRQ_HANDLED. Otherwise, the macro returns IRQ_NONE.

• irqaction
  • irq_handler_t

• /path to kernel source/kernel/irq/handle.c
  • handle_irq_event
    • irq action chain handler
    • is called in irq_flow_handler_t

IRQ flags

• Disable local interrupts while processing
  • old version
    • SA_INTERRUPT
      • unset
        • the current interrupt line disabled on all processors
      • set
        • the current interrupt line disabled on all processors
        • all interrupts on the current processor disabled
  • new version
    • IRQF_DISABLE

flow handling

• irq_flow_handler_t
• The function is responsible to use the controller-specific methods provided in chip to perform the necessary low-level actions required to process the interrupt.

• Approaches
  • edge-triggerred
    • handle_edge_irq
      • Edge-triggered IRQs are not masked when they are processed, but the handler should only be processed on a single CPU. If the IRQ_INPROGRESS flag is set, the IRQ is already being processed on another CPU. By setting the IRQ_PENDING flag, the kernel remembers that another IRQ needs to be served later. After masking the IRQ and sending an acknowledgment to the controller via mask_ack_irq, processing can be aborted.
    • IRQ_TYPE_RISING, IRQ_TYPE_FALLING, IRQ_TYPE_EDGE_BOTH
  • level-triggerred
    • handle_level_irq
      • level-triggered interrupts must be masked when they are processed.
    • IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW

• handle_fasteoi_irq
  • It is basically identical with handle_level_irq, except that interaction with the controller chip (chip->eoi) is only required at the very end.
• handle_simple_irq
  • require no flow control
• handle_percpu_irq
  • IRQs that can only happen on one specific CPU of a multiprocessor system.

registering irq/requiest_irq

• request_irq
  • create irqaction instance
  • setup_irq
    • rand_initialize_irq
    • handler->startup
    • register_irq_proc
    • register_handler_proc

• set_irq_type(2.6)
• set_external_irq(2.4)
  • edge
    • EXT_LOWLEVEL
    • EXT_HIGHLEVEL
    • EXT_FALLING_EDGE
    • EXT_RISING_EDGE
    • EXT_BOTH_EDGES
  • pullup
    • GPIO_PULLUP_DIS
    • GPIO_PULLUP_EN

freeing irq

• free_irq

• chip->shutdown

disable/enable irq

• for all CPUs
  • disable_irq
    • disables the given interrupt but also waits for a currently executing interrupt handler
  • disable_irq_nosync
  • enable_irq

• local CPU
  • local_irq_save/local_irq_restore
  • local_irq_disable
    • do { unsigned long x; local_irq_save(x); } while (0)
  • local_irq_enable

registering interrupt handlers

• /path to kernel source/arch/x86/kernel/traps.c

• Bottom Halves

Bottom Halves/BH

• No matter how many CPUs you have, no two BHs will run at the same time

• timer BH
  • (include/linux/timer.h)

• local_bh_disable/local_bh_enable
  • prevent softirqs, tasklets and bottom halves from running on the current CPU.
  • disable soft interrupts on the local CPU, and restore them.

softIRQs

• Whenever a system call is about to return to userspace, or a hardware interrupt handler exits, any ‘software interrupts’ which are marked pending (usually by hardware interrupts) are run.
• Softirqs are fully-SMP versions of BHs: they can run on as many CPUs at once as required; Softirqs can run concurrently on several CPUs, even if they are of the same type.
• Linux的内核软中断（softirq）执行分析

• kernel/softirq.c

• softirq_action

• open_softirq
• raise_softirq

tasklets

• tasklets are implemented on top of softIRQs, they are always executed when software interrupts are handled.
• A tasklet can be executed on only one processor at a time, but other tasklets may run in parallel. The same type of tasklet cannot be executed by two CPUs at the same time. However, tasklets of different types can be executed concurrently on several CPUs.
• Tasklets are also guaranteed to run on the same CPU as the function that first schedules them. Therefore, an interrupt handler can be secure that a tasklet does not begin executing before the handler has completed.
• tasklets are like softirqs, except they are dynamically-registrable.

• tasklet_action
  • The function first determines the CPU-specific list in which the tasklets marked for execution are linked. It then redirects the list header to a local element, and thus removes all entries from the public list.

Work Queue

• It allows kernel functions to be activated (much like deferrable functions) and later executed by special kernel threads called worker threads.
• work queues run in process context
• Neither deferrable functions nor functions in a work queue can access the User Mode address space of a process. Deferrable function can make no assumption about the process that is currently running when it is executed. On the other hand, a function in a work queue is executed by a kernel thread, so there is no User Mode address space to access.

• Context

Process Context

• When the kernel is running directly on behalf of a (usually) user-space process; the code which implements system calls is one example. When the kernel is running in process context, it is allowed to go to sleep if necessary.

Hardware Interrupt Context

• in_irq
  • in_irq returns TRUE if the CPU is currently serving a hardware interrupt.

Software Interrupt Context

• in_softirq
  • in_softirq returns TRUE if the CPU is currently serving a software interrupt.

Interrupt Context

• Interrupts are executed asynchronously; in other words, they can occur at any time.
• The scheduler may not be invoked in the interrupt context.
• The handler routine may not go to sleep.
• in_interrupt
  • indicate whether or not an interrupt is currently being serviced
  • either in a interrupt handler or deferrable functions(softirq or tasklet)
  • in_interrupt returns TRUE if the CPU is currently serving a hardware or software interrupt, or preemption is disabled.

Atomic Context

• Atomic context and kernel API design
  • in_atomic() has no way to know if the calling code holds any spinlocks or not

• in_atomic
  • scheduling is not allowed
  • this includes hardware and software interrupt contexts as well as any time when a spinlock is held

• rules
  1. no access to user space
  2. no sleeping