JTAG

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  • Test Access Port(TAP) controller
    • a state machine that regulates the flow of serial test patterns and results from TDI to TDO.
    • Control Signals
      • ShiftDR
        • ShiftDR controls sampling and shifting of the data in the shift register.
      • ClockDR
      • UpdateDR
  • boundary-scan register
    • The boundary-scan register communicates with all usable I/O pins, which are configured as bi-directional drivers.
    • shifts data in through Scan In on the rising edge of ClockDR when ShiftDR is asserted.
    • If the bidirectional I/O BTTLD is set as an input (OC=1), the signal present at the pin is latched into the shift register on the rising edge of ClockDR when ShiftDR is unasserted.
    • secondary register
      • If the secondary registers were eliminated, then the shift-register element might correctly drive the output control during data shifting.
  • bypass register
    • The bypass register enables data to be moved more quickly through the device by bypassing the boundary-scan register.
  • instruction register
    • The instruction register holds the test instruction that activates either the boundary-scan or bypass register, and also helps control the MUX that supplies the source for TDO.
    • The logical value loaded into the instruction register controls the multiplexer MUX that selects either the boundary-scan or bypass register to drive TDO.
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